[RTL] Synthesis optimization barriers for DCLS#472
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In OpenTitan as well as in Caliptra, prim_buf is used as a synthesis optimization barrier. It can be used to avoid that synthesis tools remove some FI hardening that is based on redundancy, e.g., DCLS. Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org>
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The changes look good. Please rebase the branch on top of current main.
It'd be good to run the whole testsuite on this (including private jobs). To do it we need to push this code to a branch in this repo and trigger the CI. I can do that for you
Thanks for the review @kgugala! I've checked, the PR is already rebased on top of the most recent main commit (4d9fdbf). The code in this PR is already pushed to a branch in this repo (https://github.com/chipsalliance/Cores-VeeR-EL2/tree/dev/nasahlpa/synthesis_optimization). Should this be sufficient to run the private jobs? |
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looks like DCLS block test is failing, can you look into that? |
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Depending on synthesis constraints and synthesis tools, some synthesis tools could potentially remove the shadow core of the DCLS feature as it always should be an identical copy of the main core. To prevent this optimiziation, use the prim_buf module on the core IOs. Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org>
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Coverage report for this PR is available at https://chipsalliance.github.io/Cores-VeeR-EL2//html/dev/472/coverage_dashboard/all, documentation is available at https://chipsalliance.github.io/Cores-VeeR-EL2//html/dev/472/docs_rendered/html |
This is now fixed and CI is all green. |
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This PR:
el2_prim_buf, which can act as synthesis optimization barriers when constraint correctlyel2_prim_bufsto prevent that aggressive synthesis optimization passes could reduce the security of the DCLS